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1 LTC4060 4060f standalone linear nimh/nicd fast battery charger complete fast charger controller for single, 2-, 3- or 4-series cell nimh/nicd batteries no firmware or microcontroller required termination by ? v, maximum voltage or maximum time no sense resistor or blocking diode required automatic recharge keeps batteries charged programmable fast charge current: 0.4a to 2a accurate charge current: 5% at 2a fast charge current programmable beyond 2a with external sense resistor automatic detection of battery precharge for heavily discharged batteries optional temperature qualified charging charge and ac present status outputs can drive led automatic sleep mode with input supply removal negligible battery drain in sleep mode: <1 a manual shutdown input supply range: 4.5v to 10v available in 16-lead dfn and tssop packages portable computers, cellular phones and pdas medical equipment charging docks and cradles portable consumer electronics , ltc and lt are registered trademarks of linear technology corporation. 2-cell, 2a standalone nimh fast charger with optional thermistor and charge indicator descriptio u features applicatio s u typical applicatio u the ltc ? 4060 is a complete fast charging system for nimh or nicd batteries. just a few external components are needed to design a standalone linear charging system. an external pnp transistor provides charge current that is user programmable with a resistor. a small external capaci- tor sets the maximum charge time. no external current sense resistor is needed, and no blocking diode is required. the ic automatically senses the dc input supply and bat- tery insertion or removal. heavily discharged batteries are initially charged at a c/5 rate before a fast charge is applied. fast charge is terminated using the C ? v detection method. backup termination consists of a programmable timer and battery overvoltage detector. an optional external ntc ther- mistor can be used for temperature-based qualification of charging. an optional programmable recharge feature au- tomatically recharges batteries after discharge. manual shutdown is accomplished with the shdn pin, while removing input power automatically puts the LTC4060 into sleep mode. during shutdown or sleep mode, battery drain is <1 a. the LTC4060 is available in both low profile (0.75mm) 16- pin 5mm 3mm dfn and 16-lead tssop packages. both feature exposed metal die mount pads for optimum ther- mal performance. 2-cell nimh charging profile v cc v in = 5v LTC4060 gnd shdn chrg ntc prog arct sel0 sel1 acp sense drive bat timer chem pause 330 ? 698 ? ntc 1.5nf 4060 ta01 nimh battery charge + charge time (minutes) 0 3.10 battery voltage (v) 3.20 3.30 3.40 10 20 30 40 4060 ta01b 50 60 C ? v termination
2 LTC4060 4060f order part number (note 1) v cc to gnd ............................................... C0.3v to 11v input voltage shdn, ntc, sel0, sel1, prog, arct, bat, chem, timer, pause ...... C0.3v to v cc + 0.3v output voltage chrg, acp, drive ................... C0.3v to v cc + 0.3v output current (sense) ...................................... C2.2a short-circuit duration (drive) ...................... indefinite LTC4060edhc absolute m axi m u m ratings w ww u package/order i n for m atio n w u u consult ltc marketing for parts specified with wider operating temperature ranges. operating ambient temperature range (note 2) ............................................. C 40 c to 85 c operating junction temperature (note 3) ........... 125 c storage temperature range tssop package ............................... C 65 c to 150 c dfn package .................................... C65 c to 125 c lead temperature (soldering, 10 sec) tssop package ................................................ 300 c 16 15 14 13 12 11 10 9 17 1 2 3 4 5 6 7 8 gnd chrg v cc acp chem ntc sel1 sel0 drive bat sense timer shdn pause prog arct top view dhc16 package 16-lead (5mm 3mm) plastic dfn t jmax = 125 c, ja = 37 c/w exposed pad (pin 17) is gnd must be soldered to pcb to obtain ja = 37 c/w otherwise ja = 140 c dhc part marking 4060 order part number LTC4060efe fe part marking 4060efe fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 drive bat sense timer shdn pause prog arct gnd chrg v cc acp chem ntc sel1 sel0 17 t jmax = 125 c, ja = 37 c/w exposed pad (pin 17) is gnd must be soldered to pcb to obtain ja = 37 c/w otherwise ja = 135 c the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v bat = 2.8v, gnd = 0v unless otherwise specified. all currents into the device pins are positive and all currents out of the device pins are negative. all voltages are referenced to gnd unless otherwise specified. electrical characteristics symbol parameter conditions min typ max units v cc supply v cc operating voltage range (note 4) 4.50 10 v i cc v cc supply current (note 9) i prog = 2ma (r prog = 698 ? ), 2.9 4.3 ma pause = v cc i sd v cc supply shutdown current shdn = 0v 250 325 a i bsd battery pin leakage current in shutdown (note 5) v bat = 2.8v, shdn = 0v C1 0 1 a i bsl battery pin leakage current in sleep (note 6) v cc = 0v, v bat = 5.6v C1 0 1 a v uvi1 undervoltage lockout exit threshold sel0 = 0, sel1 = 0 and sel0 = v cc , 4.25 4.36 4.47 v sel1 = 0, v cc increasing v uvd1 undervoltage lockout entry threshold sel0 = 0, sel1 = 0 and sel0 = v cc , 4.15 4.26 4.37 v sel1 = 0, v cc decreasing
3 LTC4060 4060f symbol parameter conditions min typ max units the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v bat = 2.8v, gnd = 0v unless otherwise specified. all currents into the device pins are positive and all currents out of the device pins are negative. all voltages are referenced to gnd unless otherwise specified. electrical characteristics v uvi2 undervoltage lockout exit threshold sel0 = 0, sel1 = v cc , v cc increasing 6.67 6.81 6.95 v v uvd2 undervoltage lockout entry threshold sel0 = 0, sel1 = v cc , v cc decreasing 6.57 6.71 6.85 v v uvi3 undervoltage lockout exit threshold sel0 = v cc , sel1 = v cc , v cc increasing 8.28 8.47 8.65 v v uvd3 undervoltage lockout entry threshold sel0 = v cc , sel1 = v cc , v cc decreasing 8.18 8.37 8.55 v v uvh undervoltage lockout hysteresis for all sel0, sel1 options 100 mv charging performance i fch high fast charge current (notes 7, 10) r prog = 698 ? , 5v < v cc < 10v 1.9 2 2.1 a i fcl low fast charge current (note 7) r prog = 3480 ? , 4.5v < v cc < 10v 0.35 0.4 0.45 a i pch high precharge current (note 7) r prog = 698 ? , 4.5v < v cc < 10v 320 400 480 ma i pcl low precharge current (note 7) r prog = 3480 ? , 4.5v < v cc < 10v 40 80 120 ma i brd battery removal detection bias current 4.5v < v cc < 10v, v bat = v cc C 0.4v C450 C300 C160 a v br battery removal threshold voltage (note 8) v cell increasing, 4.5v < v cc < 10v 1.95 2.05 2.15 v v brh battery removal threshold hysteresis voltage v cell decreasing 50 mv (note 8) v bov battery overvoltage threshold (note 8) v cell increasing, 4.5v < v cc < 10v 1.85 1.95 2.05 v v bovh battery overvoltage threshold hysteresis (note 8) v cell decreasing 50 mv v fcq fast charge qualification threshold voltage v cell increasing, 4.5v < v cc < 10v 840 900 960 mv (note 8) v fcqh fast charge qualification threshold hysteresis v cell decreasing 50 mv voltage (note 8) v idt initial delay hold-off threshold voltage (note 8) v cell increasing, 4.5v < v cc < 10v 1.24 1.3 1.36 v v idth initial delay hold-off threshold hysteresis voltage v cell decreasing 50 mv (note 8) v mdv C ? v termination (note 8) chem = v cc (nicd) 11 16 21 mv chem = 0v (nimh) 5814mv v prog program pin voltage 4.5v < v cc < 10v, r prog = 635 ? 1.45 1.5 1.54 v and 3480 ? v art automatic recharge programmed threshold v cell decreasing, v arct = 1.1v, 1.065 1.1 1.135 v voltage accuracy (note 8) 4.5v < v cc < 10v v ardt automatic recharge default threshold voltage v cell decreasing, v arct = v cc , 1.235 1.3 1.365 v accuracy (note 8) 4.5v < v cc < 10v v arh automatic recharge threshold voltage hysteresis v cell increasing 50 mv (note 8) v ardef automatic recharge pin default enable threshold v cc v cc v voltage C 0.8 C 0.2 v ardis automatic recharge pin disable threshold 250 650 mv voltage i arl automatic recharge pin pull-down current v arct = 1.3v 0.15 1.5 a v cld ntc pin cold threshold voltage v ntc decreasing, 4.5v < v cc < 10v 0.83 ? 0.86 ? 0.89 ? v v cc v cc v cc v cldh ntc pin cold threshold hysteresis voltage v ntc increasing 150 mv v hti ntc pin hot charge initiation threshold voltage v ntc decreasing, 4.5v < v cc < 10v 0.47 ? 0.5 ? 0.53 ? v v cc v cc v cc
4 LTC4060 4060f symbol parameter conditions min typ max units the indicates specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v bat = 2.8v, gnd = 0v unless otherwise specified. all currents into the device pins are positive and all currents out of the device pins are negative. all voltages are referenced to gnd unless otherwise specified. electrical characteristics v htih ntc pin hot charge initiation hysteresis voltage v ntc increasing 100 mv v htc ntc pin hot charge cutoff threshold voltage v ntc decreasing, 4.5v v cc 10v 0.37 ? 0.4 ? 0.43 ? v v cc v cc v cc v htch ntc pin hot charge cutoff hysteresis voltage v ntc increasing 100 mv v ndis ntc pin disable threshold voltage 25 250 mv i nl ntc pin pull-down current v ntc = 2.5v 0.15 1.5 a t acc timer accuracy r prog = 698 ? , c timer = 1.2nf and C15 0 15 % r prog = 3480 ? , c timer = 470pf output drivers i drv drive pin sink current v drive = 4v 40 70 120 ma r drv drive pin resistance to v cc v drive = 4v, not charging 4700 ? v ol acp, chrg output pins low voltage i acp = i chrg = 10ma 0.8 v i oh acp, chrg output pins high leakage current outputs inactive, v chrg = v acp = v cc C2 2 a control inputs v it shdn, sel0, sel1, chem, pause pins digital v cc = 10v 350 650 mv input threshold voltage v ith shdn, sel0, sel1, chem, pause pins digital 50 mv input hysteresis voltage i ipd shdn, sel0, sel1, chem pins digital input v cc = 10v, v in = v cc 0.4 2 a pull-down current i ipu pause pin digital input pull-up current v in = gnd C2 C0.4 a note 1: absolute maximum ratings only indicate limits for survivability. operating the device beyond these limits may result in permanent damage. continuous or extended application of these maximum levels may adversely affect device reliability. note 2: the LTC4060 is guaranteed to meet performance specifications from 0 c to 70 c ambient temperature range and 0 c to 85 c junction temperature range. specifications over the C40 c to 85 c operating ambient temperature range are assured by design, characterization and correlation with statistical process controls. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. overtempera- ture protection is activated at a temperature of approximately 145 c, which is above the specified maximum operating junction temperature. continuous operation above the specified maximum operation temperature may result in device degradation or failure. operating junction temperature t j (in c) is calculated from the ambient temperature t a and the average power dissipation p d (in watts) by the formula: t j = t a + ja ? p d note 4: short duration drops below the minimum v cc specification of several microseconds or less are ignored by the undervoltage detection circuit. note 5: assumes that the external pnp pass transistor has negligible b-c reverse leakage current when the collector is biased at 2.8v (v bat for two charged cells in series) and the base is biased at v cc . note 6: assumes that the external pnp pass transistor has negligible b-e reverse leakage current when the emitter is biased at 0v (v cc ) and the base is biased at 5.6v (v bat for four charged cells in series). note 7: the charge current specified is the regulated current through the internal current sense resistor that flows into the external pnp pass transistors emitter. actual battery charging current is slightly less and depends upon pnp alpha. note 8: given as a per cell voltage (v bat /number of cells). note 9: supply current includes the current programming resistor current of 2ma. the charger is paused and not charging the battery. note 10: the minimum v cc supply is set at 5v during this test to compensate for voltage drops due to test socket contact resistance and 2a of current. this ensures that the supply voltage delivered to the device under test does not fall below the uvlo entry threshold. specification at the minimum v cc of 4.5v is assured by design and characterization.
5 LTC4060 4060f typical perfor a ce characteristics uw nimh battery charging characteristics at 1c rate nicd battery charging characteristics at 1c rate nimh battery charging characteristics at c/2 rate nicd battery charging characteristics at c/2 rate i fch vs temperature and supply voltage i fcl vs temperature and supply voltage i brd vs temperature and supply voltage v mdv vs temperature and supply voltage t acc vs temperature and supply voltage charge time (minutes) 0 1.4 cell voltage (v) 1.5 1.6 1.7 10 20 30 40 4060 g02 50 60 C ? v termination t a = 25 c charge time (minutes) 020 1.35 cell votlage (v) 1.45 1.60 40 80 100 4060 g03 1.40 1.55 1.50 60 120 140 C ? v termination t a = 25 c charge time (minutes) 020 1.40 cell votlage (v) 1.50 1.65 40 80 100 4060 g04 1.45 1.60 1.55 60 120 140 C ? v termination temperature ( c) C50 1.990 i fch (a) 1.995 2.000 2.005 2.010 C25 0 25 50 4060 g05 75 100 125 v cc = 10v v cc = 4.5v temperature ( c) C50 398 i fcl (ma) 399 400 401 402 C25 0 25 50 4060 g06 75 100 125 v cc = 10v v cc = 4.5v temperature ( c) C50 C340 i brd ( a) C300 C260 C25 0 25 50 4060 g07 75 100 125 v cc = 10v v cc = 4.5v temperature ( c) C50 12 14 18 25 75 4060 g08 10 8 C25 0 50 100 125 6 4 16 v mdv (mv) nicd 4.5v v cc 10v nimh 4.5v v cc 10v temperature ( c) C50 0.5 1.0 1.7 25 75 4060 g09 0 C0.5 C25 0 50 100 125 C1.0 C1.5 1.5 error (%) v cc = 10v v cc = 4.5v r prog = 3480 ? c timer = 470pf r prog = 698 ? c timer = 1.2nf charge time (minutes) 0 1.55 cell voltage (v) 1.60 1.65 1.70 10 20 30 40 4060 g01 50 60 C ? v termination t a = 25 c
6 LTC4060 4060f uu u pi fu ctio s drive (pin 1): base drive output for the external pnp pass transistor. provides a controlled sink current that drives the base of the pnp. this pin has current limit protection for the LTC4060. bat (pin 2): battery voltage sense input pin. the LTC4060 uses the voltage on this pin to monitor battery voltage and control the battery current during charging. an internal resistor divider is connected to this pin which is discon- nected when in shutdown or when no power is applied to v cc . sense (pin 3): charge current sense node input. current from v cc passes through the internal current sense resis- tor and reappears at the sense pin to supply current to the external pnp emitter. the pnp collector provides charge current directly to the battery. timer (pin 4): charge timer input. a capacitor connected between timer and gnd along with a resistor connected from prog to gnd programs the charge cycle timing limits. shdn (pin 5): active low shutdown control logic input. when pulled low, charging stops and the LTC4060 supply current is minimized. pause (pin 6): pause enable logic input. the charger can be paused, turning off the charge current, disabling termi- nation and stopping the timer when this pin is high. a low level will resume the charging process. prog (pin 7): charge current programming input. pro- vides a virtual reference of 1.5v for an external resistor (r prog ) tied between this pin and gnd that programs the battery charge current. the fast charge current will be 930 times the current through this resistor. this voltage is also usable as system voltage reference. arct (pin 8): autorecharge threshold programming input. when the average cell voltage falls below this threshold, charging is reinitiated. the voltage on this pin is conveniently derived by using two series prog pin resistors and connecting to their common. connecting arct to v cc invokes a default threshold of 1.3v. connect- ing arct to gnd inhibits autorecharge. sel0, sel1 (pins 9, 10): number of cells selection logic input. for single cell, connect both pins to gnd. for two cells, connect sel1 to gnd and sel0 to v cc. for three cells, sel1 connects to v cc and sel0 to gnd. for four cells, connect both pins to v cc . ntc (pin 11): battery temperature input. an external ntc thermistor network may be connected to ntc to provide temperature-based charge qualification. connecting ntc to gnd inhibits this function. chem (pin 12): battery chemistry selection logic input. when connected to a high level nicd fast charge C ? v termination parameters are used. a low level selects nimh parameters. acp (pin 13): open-drain power supply status output. when v cc is greater than the undervoltage lockout thresh- old, the acp pin will pull to ground. otherwise the pin is high impedance. this output is capable of driving an led. v cc (pin 14): power input. this pin can be bypassed to ground with a capacitance of 1 f. chrg (pin 15): open-drain charge indicator status out- put. the LTC4060 indicates it is providing charge to the battery by driving this pin to gnd. if charging is paused or suspended due to abnormal battery temperature, the pin remains pulled to gnd. otherwise the pin is high imped- ance. this output can drive an led. gnd (pin 16): ground. this pin provides a ground for the internal voltage reference and other circuits. all voltage thresholds are referenced to this pin. exposed pad (pin 17): thermal connection. internally connected to gnd. solder to pcb ground for optimum thermal performance.
7 LTC4060 4060f block diagra w 7 C + a1 r1 31.5 ? r2 0.03 ? 1.5v prog r prog 14 v cc ntc cutoff i i/5 hot cold current divider voltage reference uvlo supply good sel0 sel1 autorecharge detector ic overtemperature detect output driver and current limit battery detector a/d converter i brd 4060 bd oscillator timer c timer i osc thermistor interface charger state control logic v cc i i/5 i osc C + 11 chrg 15 acp 13 shdn 5 pause 6 4 arct 8 2 sel0 9 sel1 10 chem gnd 16, 17 12 bat 1 drive 3 sense a2 +
8 LTC4060 4060f operatio u the LTC4060 is a complete linear fast charging system for nimh or nicd batteries. operation can be understood by referring to the block diagram, state diagram (figure 1) and application circuit (figure 2). while in the unpowered sleep mode, the battery is disconnected from any internal loading. the sleep mode is exited and the shutdown mode is entered when v cc rises above the uvlo (undervoltage lock out) exit threshold. the uvlo thresholds are depen- dent upon the number of series cells programmed by the sel0 and sel1 pins. when shutdown occurs the acp pin goes from a high to low impedance state. the shutdown mode is exited and the charge qualification mode entered when all of the following conditions are met: 1) there is no manual shutdown command from shdn, 2) the battery overvoltage detector does not detect a battery overvolt- age, 3) the battery removal detector detects a battery in place, 4) pause is inactive and 5) the ics junction tempera- ture is normal. once in the charge qualification mode the thermistor interface monitors an optional thermistor net- work to determine if the battery temperature is within charging limits. if the temperature is found within limits charging can begin. while charging, the chrg pin pulls to gnd which can drive an led. charge qualification battery present and temperature good (optional) shutdown sleep supply good (acp = 0) low or no supply manual shutdown (shdn = 0) adequate supply and charger enabled battery removed, battery overvoltage, charge period timed out or ic too hot precharge (i max /5) fast charge (i max ) automatic recharge C ? v termination 4060 f01 adequate v cell and temperature good (optional) v cell < autorecharge threshold figure 1. LTC4060 basic state diagram
9 LTC4060 4060f the charge current is set with an external current pro- gramming resistor connected between the prog pin and gnd. in the block diagram, amplifier a1 will cause a virtual 1.5v to appear on the prog pin and thus, all of the pro- gramming resistors current will flow through the n-channel fet to the current divider. the current divider is controlled by the charger state control logic to produce a voltage across r1, appropriate either for precharge (i/5) or for fast charge (i), depending on the cell voltage. the current di- vider also produces a constant current i osc , that along with an external capacitor tied to the timer pin, sets the oscillators clock frequency. during charging, the external pnp transistors collector will provide the battery charge current. the pnps emitter current flows into the sense pin and through the internal current sense resistor r2 (0.03 ? ). this current is slightly more than the collector current since it includes the base current. amplifier a2 and the output driver will drive the base of the external pnp through the drive pin to force the same reference voltage that appears across r1 to appear across the r2. the pre- cision ratio between r1 and r2, along with the current programming resistor, accurately determines the charge current. when charging begins, the charger state control logic will enable precharge of the battery. when the cell voltage exceeds the fast charge qualification threshold, fast charge begins. if the cell voltage exceeds the initial delay hold off threshold voltage just prior to precharge, then the a/d converter immediately monitors for a C ? v event to terminate charging while in fast charge. otherwise, the fast charge voltage stabilization hold off period must expire before the a/d converter monitors for a C ? v event from which to terminate charging. the C ? v magnitude for termination is selected for either nimh or nicd by the chem pin. should the battery temperature become too hot or too cold, charging will be suspended by the charger state control logic until the temperature enters normal limits. a termination timer puts the charger into shutdown mode if the programmed time has expired. after charging has ended, the optional autorecharge detector function monitors for the battery voltage to drop to either a default or externally programmed cell voltage before automati- cally restarting a charge cycle. the shdn pin can be used to return the charger to a shutdown and reset state. the pause pin can be used to pause the charge current and internal clocks for any interval desired. fault conditions, such as overheating of the ic due to excessive pnp base current drive, are monitored and limited by the ic overtemperature detection and output driver and current limit blocks. when either v cc is removed or manual shutdown is entered, the charger will draw only tiny leakage currents from the battery, thus maximizing standby time. with v cc removed, the external pnps base is connected to the battery by the charger. in manual shutdown, the base is connected to v cc by the charger. undervoltage lockout an internal undervoltage lockout circuit (uvlo) monitors the input voltage and keeps the charger in the inactive sleep mode until v cc rises above the undervoltage exit threshold. the acp pin is high impedance while in the sleep mode and becomes low impedance to ground when in the active mode. the threshold is dependent upon the number of series cells selected by the sel0 and sel1 pins (see v uvi1-3 and v uvd1-3 in the electrical characteristics table). the uvlo circuit has a built-in hysteresis of 100mv. the thresholds are chosen to provide a minimum voltage drop of approximately 600mv between minimum v cc and bat at a battery cell voltage of 1.8v. this helps to protect against excessive saturation in the external power pnp when the supply voltage is near its minimum. while inactive the LTC4060 reduces battery current to just a negligible leakage current (i bsl ). manual shutdown control the LTC4060 can be forced into a low quiescent current shutdown while v cc is present by applying a low level to the shdn pin. in manual shutdown, charging is inhibited, the internal timer is reset and oscillator disabled, chrg status output is high impedance and acp continues to provide the correct status. the LTC4060 will draw low cur- rent from the supply (i sd ), and only a negligible leakage current is applied to the battery (i bsd ). if a high level is operatio u
10 LTC4060 4060f table 1. LTC4060 time limit programming examples typical battery charge battery automatic fast voltage time voltage recharge uvlo exit, battery fast charge stabilization limit sampling entry insertion/removal/overvoltage, charge rate hold off (t max ) interval delay fast charge entry and current r prog c timer (c) (minutes) (hours) (seconds) (seconds) thermistor event delays (ms) 2a 698 ? 1nf 1.5 4.6 to 5.7 1.1 15 15 to 31 175 to 260 2a 698 ? 1.5nf 1 6.9 to 8.4 1.6 23 23 to 46 260 to 390 2a 698 ? 1.8nf 0.75 8.4 to 10.3 2 28 28 to 56 320 to 480 2a 698 ? 2.7nf 0.5 12.6 to 15.4 3 42 42 to 84 480 to 720 400ma 3480 ? 180pf 1.5 4.2 to 5.2 1 14 14 to 28 160 to 240 400ma 3480 ? 270pf 1 6.3 to 7.7 1.5 21 21 to 42 240 to 360 400ma 3480 ? 390pf 0.75 8.9 to 11 2.1 30 30 to 60 340 to 510 400ma 3480 ? 560pf 0.5 12.6 to 15.4 3 42 42 to 84 480 to 720 operatio u applied to the shdn pin, shutdown ends and charge quali- fication is entered. charge qualification after exiting the sleep or shutdown modes the LTC4060 will check for the presence of a battery and for proper battery temperature (if a thermistor is used) before initiat- ing charging. when v cell (v bat /number of cells) is below 2.05v (v br ), a battery is assumed to be present. should v cell rise above 1.95v (v bov ) for a time greater than the battery overvoltage event delay shown in the far right column of table 1, then a battery overvoltage condition is detected and charging stops. once stopped in this way, qualifica- tion can be reinitiated after v cell has fallen below 1.9v (v bov C v bovh ) only by removing and replacing the battery (or replacing the battery if the overvoltage condition is a result of battery removal), toggling the shdn pin low to high or removing and reapplying power to the charger. if the ntc pin voltage is above the temperature disable threshold (v ndis ), the LTC4060 verifies that the ther- mistor temperature is between 5 c and 45 c. charging will not initiate until these temperature limits are met. the LTC4060 continues to qualify important voltage and temperature parameters during all charging states. if v cc drops below the undervoltage lockout threshold, sleep mode is entered. if the internal die temperature becomes excessive, charg- ing stops and the part enters the shutdown state. once in the shutdown state charge qualification can be reinitiated only when the die temperature drops to normal and then by removing and replacing the battery or toggling the shdn pin low to high or removing and reapplying power to the charger. precharge the state that is entered when qualified charging begins is precharge. the chrg status output is set low and remains low during both precharge and fast charge. if the voltage on v cell is below the 900mv (v fcq ) fast charge qualifica- tion voltage, the LTC4060 charges using one-fifth the maximum programmed charge current. the cell voltage is continuously checked to determine when the battery is ready to accept a fast charge. until this voltage reaches v fcq , the LTC4060 remains in precharge. if an external thermistor indicates that the sensed tem- perature is beyond a range of 5 c to 45 c charging is suspended, the charge timer is paused and the chrg status output remains low. normal charging resumes from the previous state when the sensed temperature rises above 5 c or falls below 45 c. fast charge when the average cell voltage exceeds v fcq , the LTC4060 transitions from the precharge to the fast charge state and
11 LTC4060 4060f operatio u charging begins at the maximum current set by the exter nal programming resistor connected between the prog pin and gnd. if an external thermistor indicates sensed temperature is beyond a range of 5 c to 55 c charging is suspended, the charge timer is paused and the chrg status output remains low. normal charging resumes from the previous state when the sensed temperature rises above 5 c or falls below 45 c. voltage-based termination (C ? v) is then reset and immediately enabled. if voltage-based termina- tion was imminent when the temperature limits were exceeded, charge termination will occur. charge termination once fast charge begins and after an initial battery voltage stabilization hold-off period shown in table 1, voltage- based termination (C ? v) is enabled. this period is used to prevent falsely terminating on a C ? v event that can occur almost immediately after initiating charging on some heavily discharged or stored batteries. however, if v cell was measured to be above 1.3v (v idt ) immediately prior to the precharge cycle, then a mostly charged battery is assumed and voltage-based termination (C ? v) is enabled without delay. an internal 1.5mv resolution a/d converter measures the cell voltage after each battery voltage sampling interval indicated in table 1. the peak cell voltage is stored and compared to the current cell voltage. when the cell voltage has dropped by at least v mdv (magnitude selected by the chem pin) from the peak for four consecutive battery voltage sampling intervals, charging is terminated. back-up termination is provided by the charge time limiter, whose time limit is indicated in table 1, and by a battery overvoltage detector. once terminated by back-up termi- nation, charge qualification can be reinitiated only by remov- ing and replacing the battery or toggling the shdn pin low to high or removing and reapplying power to the charger. automatic recharge once charging is complete, the optional programmable automatic recharge state can be entered. this state, if enabled, will automatically restart the charger from the charge qualification state without user intervention when- ever the battery cell voltage drops below a set level. with the advent of low memory effect nimh and improved nicd cells an automatic recharge feature is practical and elimi- nates the need for very slow trickle charging. the chrg status output is high impedance in the auto- matic recharge state until charging begins. if the v cell voltage drops below the voltage set on the arct pin for at least the automatic recharge entry delay time as shown in table 1, the charge qualification state is entered and charging will begin anew in fast charge. an easy way of setting the voltage on the arct pin is by using two series current programming resistors and connecting their com- mon to the arct pin as shown in figure 2. the prog pin will provide a constant 1.5v (v prog ). the programmable voltage range of the arct pin is approximately 0.8v to 1.6v. a preprogrammed recharge threshold of 1.3v (v ardt ) is selected when the arct pin is connected to v cc (v ardef ). automatic recharge is disabled when the arct pin is connected to ground (v ardis ). pause after charging is initiated, the pause pin may be used to pause operation at any time. whenever the voltage on the pause pin is a logic high, the charge timer and all other timers pause, charging is stopped and the fast charge ter- mination algorithm is inhibited. the chrg status output remains at gnd. if voltage-based termination was immi- nent before pause, charge termination will occur. otherwise, when pause ends, the charge timer and all other timers resume timing, charging restarts and voltage-based termi- nation (C ? v) is reset and immediately enabled. if the bat- tery is removed while the pause pin is a logic high, then battery removal is detected and shutdown is entered. if the battery is replaced while the pause pin is a logic high, it will not be detected until pause is turned off. for pause periods or a series of periods where the battery capacity could be significantly depleted, consider using shutdown instead of pause to avoid having the safety timer expire before the battery can be fully charged. shutdown resets the safety timer.
12 LTC4060 4060f table 2. LTC4060 charging parameters state chem charge time limit t min t max i chrg typical termination condition precharge both t max 5 c45 ci max /5 v cell 0.9v fast charge nicd t max 5 c55 ci max C16mv per cell after initial t max /12 delay nimh t max 5 c55 ci max C8mv per cell after initial t max /12 delay battery chemistry selection the desired battery chemistry is selected by programming the chem pin to the proper voltage. when wired to gnd, a set of parameters specific to charging nimh cells is selected. when chem is connected to v cc , charging is optimized for nicd cells. the various charging parameters are detailed in table 2. cell selection the number of series cells is selected using the sel0 and sel1 pins. for one cell, both pins connect to gnd. for two cells, sel0 connects to v cc and sel1 to gnd. for three cells, sel0 connects to gnd and sel1 to v cc . for four cells, both connect to v cc . insertion and removal of batteries the LTC4060 automatically senses the insertion or re- moval of a battery by monitoring the v cell pin voltage. either the charge current, or if not charging then an internal pull-up current (i brd ), will pull v cell up when the battery is removed. when this voltage rises above 2.05v (v br ) for a time greater than the battery removal event delay shown in table 1, the LTC4060 considers the battery to be absent. inserting a battery, causing v cell to fall below both v br and 1.95v (v bov ) for a period longer than the battery insertion event delay shown in table 1, results in the LTC4060 recognizing a battery present and initiates a completely new charge cycle beginning with charge qualification. all battery currents are inhibited while in shutdown. operatio u applicatio s i for atio wu uu programming charge current the battery charge current is set with an external program resistor connected from the prog pin to gnd. the for- mula for the battery fast charge current or i max is: ii v r or r i max prog prog prog max = () = ? ? ? ? ? ? = ? . ? 930 15 930 1395 where r prog is the total resistance from the prog pin to ground. for example, if 1a of fast charge current is required: r a k prog == 1395 1 14 . 1% resistor under precharge conditions, the current is reduced to 20% of the fast charge value (i max ).the LTC4060 is designed for a maximum current of 2a. this translates to a maximum prog pin current of 2.15ma and a minimum program resistor of 698 ? . reduced accuracy at low current limits the useful fast charge current to a minimum of approximately 200ma. errors in the charge current can be statistically approximated as follows: one sigma error ? 7ma for best stability over temperature and time, 1% metal- film resistors are recommended. capacitance on the prog pin should be limited to about 75pf to insure adequate ac phase margin for its amplifier. different charge currents can be programmed by various means such as by switching in different program resis- tors. a voltage dac connected through a resistor to the prog pin or a current dac connected in parallel with a
13 LTC4060 4060f resistor to the prog pin can also be used to program current. note that this will alter the timer periods unless alternate timer pin capacitors are also programmed through an analog switch. the prog pin provides a reference voltage of 1.5v (v prog ) that may be tapped for system use. current loading on prog is multiplied by 930 and appears as increased i max. this may be compensated by adjustment of r prog . total prog pin current must be limited to 2.3ma otherwise absolute maximum ratings will be exceeded. when the LTC4060 is in the shutdown mode, the prog pin is forced to ground potential to save power. programming the timer all LTC4060 internal timing is derived from the internal oscillator that is programmed with an external capacitor at the timer pin. the time periods shown in table 1 scale directly with the timer period. the programmable safety timer is used to put a time limit on the entire charge cycle for the case when charging has not otherwise terminated. the time limit is programmed by an external capacitor at the timer pin and is also dependent on the current set by the programming resistor connected to the prog pin. the time limit is determined by the following equation: t max (hours) = 1.567 ? 10 6 ? r prog ( ? ) ? c timer (f) cf t hours r timer max prog () () .? ? () = ? 1 567 10 6 some typical timing values are detailed in table 1. the timer begins at the start of a charge cycle. after the time- out occurs, the charge current stops and the chrg output assumes a high impedance state to indicate that the charging has stopped. excessively short time-out periods may not allow enough time for the battery to receive full charge or may result in premature C ? v termination due to too short a battery voltage stabilization hold-off period. excessively long time- out periods may indicate too low a charge current which may not allow voltage-based termination (C ? v) to work properly. time-out limits of less than 0.75 hour for faster 2c charge rates, or more than 3.5 hours for slower c/2 applicatio s i for atio wu uu charge rates, are generally not recommended. consult the battery manufacturer for recommended periods. an external timing source can also be used to drive the timer pin for precise or programmed control. the high level must be between 2.5v and v cc and the low level must be between 0v and 0.25v. also, the driving source must be able to overdrive the internal current source and sink which is 5% of the current through r prog . battery temperature sensing temperature sensing is optional in LTC4060 applications. to disable temperature qualification of all charging opera- tions, the ntc pin must be wired to ground. a circuit for temperature sensing using a thermistor with a negative temperature coefficient (ntc) is shown in figure 2. inter- nally derived v cc proportional voltages (v cld , v hti , v htc ) are compared to the voltage on the ntc input pin to test the temperature thresholds. the battery temperature is mea- sured by placing the thermistor close to the battery pack. in figure 2, a common 10k ntc thermistor such as a murata nth4g series nth4g39a103f can be used. r hot should be a 1% resistor with a value equal to the value of the chosen ntc thermistor at 45 c (v ntc = v hti = 0.5 ? v cc typ). another temperature may be chosen to suit the battery requirements. the LTC4060 will not initiate a charge cycle or continue with a precharge if the value of the thermistor falls below 4.42k which is a temperature rising to approximately 45 c. however, once fast charging is in progress, it will not be stopped until the thermistor drops below 3k which is a temperature rising to approximately 55 c (v ntc = v htc = 0.4 ? v cc typ). once reaching this charge cutoff threshold, charging is suspended until the value of the thermistor rises above approximately 4.8k (falling temperature) or approximately 43 c (45 c C 2 c hysteresis at v cc = 5v) and then charging is resumed. hysteresis avoids possible oscillation about the trip points. note that the comparator hysteresis voltages are constant and when v cc increases the signal level from the ther- mistor increases thus making the temperature hysteresis look smaller. during suspension the charge current is turned off and the safety timer is frozen. the LTC4060 is also designed to suspend when the thermistor rises above 34k (falling
14 LTC4060 4060f temperature) at approximately 0 c (5 c C 5 c hysteresis at v cc = 5v) and then resume when the thermistor falls below 27k (rising temperature) which will be approxi- mately 5 c (v ntc = v cld = 0.86 ? v cc typ). many thermistors with an r cold to r hot ratio of approxi- mately 7 will work. for lower power dissipation higher values of thermistor resistance can be used. the murata nth4g series offers resistances of up to 100k at 25 c. it is important that the thermistor be placed in close contact with the battery and away from the external pnp pass transistor to avoid excessive temperature errors on the sensed battery temperature. furthermore, since v cc is a high current path into the LTC4060, it is essential to minimize voltage drops between the v cc supply pin and the top of r hot by kelvin connecting r hot directly to the v cc pin. power requirements the dc power input to the v cc pin must always be within proper limits while charging a battery. voltages beyond the absolute maximum ratings may damage the charger and voltages falling below the uvlo entry thresholds, as programmed by the sel0 and sel1 pins, will likely cause the charger to enter the shutdown state (when the uvlo exit threshold is exceeded charging will begin anew). while the LTC4060 is designed to reject 60hz or 120hz supply ripple, certain precautions are required. the instantaneous ripple voltage must always be within the above mentioned limits. ripple voltage seen across the collector-base junc- tion of the external pnp pass transistor will slightly modu- late its beta and hence its base current. since the emitter current is precisely regulated by the LTC4060, any modu- lation of base current will appear at the collector. this slightly modulated battery charge current into a battery will usually produce an insignificant modulation voltage at the battery. however, if excessive wire impedance to the battery from the pnp exists, then it may be helpful to kelvin connect the bat pin to a convenient point closest to the battery to reduce ripple magnitude entering the LTC4060s battery monitoring circuits. the battery ground imped- ance should also be managed to limit ripple voltage at the bat pin. excessive ripple into the bat pin may cause the charger to deviate from specified performance. applicatio s i for atio wu uu v cc bypass capacitor a 1 f capacitor located close to the LTC4060 will usually provide adequate input bypassing. however, caution must be exercised when using multilayer ceramic capacitors. because of the self-resonance and high q characteristics of some types of ceramic capacitors, along with wiring inductance, high voltage transients can be generated under some conditions such as connecting or disconnect- ing a supply input to a hot power source. to reduce the q and prevent these transients from exceeding the absolute maximum voltage rating, consider adding about 1 ? of resistance in series with the ceramic input capacitor. bat bypass capacitor this optional capacitor, connected between bat and gnd, can be used to help filter excessive contact bounce during the battery monitoring or charging process. the value will depend upon the contact bounce open duration, but is typi- cally 10 f. another purpose of this capacitor is to bypass transient battery load events that might otherwise disrupt monitoring or charging. should the battery connections not be subject to excessive contact bounce or excessive bat- tery voltage transients, then no bat pin capacitor is re- quired. the same caution mentioned above for the v cc by- pass capacitor applies. external pnp transistor the external pnp pass transistor must have adequate beta and breakdown voltages, low saturation voltage and suf- ficient power dissipation capability that may include heat sinking. to provide 2a of charge current with the minimum avail- able base current drive of 40ma (i drv min) requires a minimum pnp beta of 50. the transistors collector to emitter breakdown voltage must be high enough to withstand the difference between the maximum supply voltage and minimum battery volt- age. almost any transistor will meet this requirement. additionally, when no power is supplied to the charger (v in = 0v and v sense = 0v), the transistors emitter to base breakdown voltage must be high enough to prevent a leakage path at the maximum battery voltage while not
15 LTC4060 4060f applicatio s i for atio wu uu charging (the drive pin is internally switched to the bat pin). most transistors will meet this requirement as well. with low supply voltages, the pnp saturation voltage (v cesat ) becomes important. the v cesat must be less than the minimum supply voltage minus the maximum voltage drop across the internal current sense resistor and bond wires (approximately 0.08 ? ) and maximum battery voltage presented to the charger accounting for wire i ? r drops. v cesat (v) < v dd(min) C (i bat(max) ? 0.08 ? + v bat(max) ) for example, if it were desired to have a programmed charge current of 2a with a minimum supply voltage of 4.75v and a maximum battery voltage of 3.6v (2 series cells at 1.8v each), then the minimum operating v cesat is: v cesat (v) = 4.75 C (2 ? 0.08 + 3.6) = 0.99v if the pnp transistor cannot achieve the saturation voltage required, base current will dramatically increase. this is to be avoided for a number of reasons: drive pin current may reach current limit resulting in the LTC4060 charac- teristics going out of specifications, excessive power dissipation may force the ic into thermal shutdown, or the battery could discharge because some of the current from the drive pin could be pulled from the battery through the forward biased pnp collector base junction. the actual battery fast charge current (i bat ) is slightly less than the regulated charge current because the charger senses the emitter current and the battery charge current will be reduced by the base current. in terms of (i c /i b ) i bat can be calculated as follows: ia i bat prog () ? = + ? ? ? ? ? ? 930 1 if = 100 then i bat is 1% low. the 1% loss can be easily compensated for by increasing i prog by 1%. another important factor to consider when choosing the pnp pass transistor is its power handling capability. the transistors data sheet will usually give the maximum rated power dissipation at a given ambient temperature with a power derating for elevated temperature operation. the maximum power dissipation of the pnp when charging is: p d(max) (w) = i max (v dd(max) C v bat(min) ) v dd(max) is the maximum supply voltage and v bat(min) is the minimum battery voltage when discharged, but not less than 0.9v/cell since less than 0.9v/cell invokes precharge current levels. thermal considerations internal overtemperature protection is provided to prevent excessive LTC4060 die temperature during a fault condi- tion. if the internal die temperature exceeds approximately 145 c, charging stops and the part enters the shutdown state. the faults can be generated from insuffient heat sinking, a shorted drive pin or from excessive drive pin current to the base of an external pnp transistor if its in deep saturation from a very low v ce . once in the shutdown state, charge qualification can be reinitiated only by re- moving and replacing the battery or toggling the shdn pin low to high or removing and reapplying power to the charger. this protection is not designed to prevent over- heating of the pnp pass transistor. indirectly though, self- heating of the pnp thermally conducting to the LTC4060 can result in the ics junction temperature rising above 145 c, thus cutting off the pnps base current. this action will limit the pnps junction temperature to some tempera- ture well above 145 c. the user should insure that the maximum rated junction temperature is not exceeded under any normal operating condition. see package/order information for the ja of the LTC4060 exposed pad packages. the actual thermal resistance in the application will vary depending on forced air cooling, use of the exposed pad and other heat sinking means, especially the amount of copper on the pcb to which the LTC4060 is attached. the majority of the power dissipated within the LTC4060 is in the current sense resitor and drive pin driver as given below: p d = (i bat ) 2 ? 0.08 + i drive (v cc C v eb ) t j = t a + ja ? p d v eb is the emitter to base voltage of the external pnp.
16 LTC4060 4060f typical applicatio s u full featured 2a charger application figure 2 shows an application that utilizes the optional temperature sensing and optional externally program- mable automatic recharge features. it also has leds to indicate charging status and the presence of sufficient input supply voltage. the prog pin has a total resistance of 691 ? to ground that programs the fast-charge current at the pnps emitter to 2.02a (2a at the collector for beta of 100). the arct pin voltage is programmed to 1.25v. when the battery cell voltage falls below this automatic recharge will begin. optional capacitor c bat filters excessive contact bounce. this circuit can be modified to charge a 4a-hr battery at a c/2 rate simply by doubling the c timer capacitance. power path control proper power path control is an important consideration when fast charging nickel cells. this control ensures the system load remains powered at all times, but that normal system operation and associated load transients do not adversely affect the charging procedure. figure 3 illus- trates a 1a charger with power path control. when v in is applied the forward biased schottky diode will power the load while the p-channel fet will disconnect the battery from the load. when v in is removed, the fet will turn-on to provide a low loss switch from the battery to the load, and the diode will isolate v in . the acp output signals the presense of v in . v cc v in = 5v LTC4060 gnd shdn chrg ntc prog arct sel0 sel1 acp sense drive bat timer chem pause 5 15 11 7 8 9 10 13 3 1 2 4 12 6 r led 330 ? r led 330 ? r hot 4.42k r ntc 10k r prog 115 ? r arct 576 ? c timer 1.5nf 16 14 4060 f02 c bat 10 f 2-cell nimh battery charge ac mjd210 + v cc v in = 5v fdg312p b220a LTC4060 gnd shdn chrg ntc prog arct sel0 sel1 acp sense drive bat timer chem pause r led 330 ? r prog 1400 ? c timer 820pf 16 r ac 10k 4060 f03 c load 10 f *drain source diode of mosfet 2-cell nimh battery charge fzt948 acp to load * 5 15 11 7 8 9 10 13 3 1 2 4 12 6 + figure 2. full featured 2a charger application figure 3. 1a charger application with power path control
17 LTC4060 4060f trickle charge the trickle charge function is normally not required due to the automatic recharge feature. however, the LTC4060 does provide a modest pull-up current (i brd ) as part of its battery removal detection method. if additional current is required for trickle charge or to support battery removal detection with current loads greater than i brd , then the simple circuit of figure 4 will facilitate that. the diode insures no reverse discharge current when v in is removed and the resistor sets the trickle current. extending charge current extending the charge current beyond 2a can be accom- plished by paralleling an external current sense resistor, r iset, with the internal current sense resistor as shown in figure 5. bond wire, lead frame and pcb interconnect resistance and mismatches in the two sense resistors value will cause charge current variability to increase in proportion to the extension in current. resistor r iset should be connected directly to the LTC4060 to reduce errors. the total current sense resistor, bond wire and lead frame resistance is approximately 0.08 ? (t.c. ? 3500ppm/ c). the formula for extended fast charge current is: ii r aa max ext max iset () ? . ?. =+ ? ? ? ? ? ? == 1 008 2153 for r iset = 0.16 ? and r prog = 698 ? . adequate pnp beta is required to meet the drive pin capability and the increased pnp power dissipation will require additional heat sinking. typical applicatio s u v cc v in 1n4001 LTC4060 sense drive bat 4060 f04 2-cell nimh battery 3.3k 3 14 1 2 + v cc v in LTC4060 sense drive bat 4060 f05 2-cell nimh battery r iset 0.16 ? 0.08 ? 3 14 1 2 + figure 4. adding trickle charge figure 5. extended charge current operation
18 LTC4060 4060f reverse input voltage protection in some applications protection from reverse supply volt- age is desired. if the supply voltage is high enough, a series blocking diode can be used. in other cases, where the voltage drop must be kept very low, a p-channel fet as shown in figure 6 can be used. typical applicatio s u * v cc *drain bulk diode of mosfet LTC4060 4060 f06 14 v in figure 6. low loss reverse input voltage protection
19 LTC4060 4060f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. u package descriptio dhc package 16-lead plastic dfn (5mm 3mm) (reference ltc dwg # 05-08-1706) 3.00 0.10 (2 sides) 5.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wjed-1) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom viewexposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.20 typ 4.40 0.10 (2 sides) 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 C 0.05 (dhc16) dfn 1103 0.25 0.05 pin 1 notch 0.50 bsc 4.40 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.20 0.05 0.50 bsc 0.65 0.05 3.50 0.05 package outline 0.25 0.05
20 LTC4060 4060f ? linear technology corporation 2004 lt/tp 0904 1k ? printed in the usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com u package descriptio fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc part number description comments ltc1732 lithium-ion linear battery charger controller simple charger uses external fet, features preset voltages, c/10 charger detection and programmable timer, input power good indication ltc1733 monolithic lithium-ion linear battery charger standalone charger with programmable timer, up to 1.5a charge current ltc1734 lithium-ion linear battery charger in thinsot tm simple thinsot charger, no blocking diode, no sense resistor needed ltc1734l lithium-ion linear battery charger in thinsot low current version of ltc1734; 50ma i chrg 180ma ltc1998 lithium-ion low battery detector 1% accurate 2.5 a quiescent current, sot-23 ltc4006/ltc4007 4a multicell li-ion battery chargers standalone charger, 6v v in 28v, up to 96% efficiency, 0.8% charging voltage accuracy ltc4008 4a multichemistry battery charger synchronous operation for high efficiency, ac adapter current limit ltc4052 monolithic lithium-ion battery pulse charger no blocking diode or external power fet required, 1.5a charge current ltc4053 usb compatible monolithic li-ion battery charger standalone charger with programmable timer, up to 1.25a charge current ltc4054 standalone linear li-ion battery charger thermal regulation prevents overheating, c/10 termination, in thinsot c/10 indicator, up to 800ma charge current ltc4055 usb power controller and li-ion battery charger charges directly from usb or wall adapter, new topology charges faster an d more efficiently ltc4058 standalone li-ion linear charger in dfn up to 950ma charge current, kelvin sense for high accuracy, ltc4058x c/10 charge termination ltc4411 low loss powerpath tm controller in thinsot automatic switching between dc sources, load sharing, ltc4412 replaces oring diodes thinsot and powerpath are trademarks of linear technology corporation. related parts

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